It is well known that integrated circuits (IC's), if they are going to fail, tend to fail early in their projected lives. To identify and eliminate such fragile IC's, IC manufacturers typically expose their integrated circuits to conditions that tend to induce such premature failure. This is known as burn-in, and the typical conditions to which the integrated circuits are exposed during burn-in are elevated temperatures together with the simultaneous application of electrical signals to the integrated circuits. The elevated temperature and the applied signals may exceed normal operating parameters. Once an integrated circuit has passed a test during or after burn-in, the chances of it functioning throughout its intended service life are greatly increased.
Burn-in may be done at various times. In many cases, burn-in is done when the IC is in its final packaged form. In such a case, the IC is plugged into a circuit board that allows the required electrical signals to be applied to the IC. Burn-in of packaged IC's has the advantage that the packaged IC is much less sensitive to physical damage or contamination, and can easily be plugged into the burn-in circuit board to make the required connections. Disadvantages of burning-in packaged IC's are that the added expense of packaging the IC is lost if the IC fails during burn-in, that there are many more individual components to handle, and that the same die type may end up in a number of different package types requiring different fixtures for burn-in.
Another burn-in option is to put individual dies into reusable packages, and then burn-in the die in the reusable package in a similar manner to the burn-in of packaged IC's. This method has the advantage that less has been invested in the IC at this time, but has the disadvantage that the individual dies are difficult to handle conveniently, and are susceptible to damage or contamination.
The cartridge of the invention is used for wafer-level burn-in. That is, the integrated circuit wafer undergoes burn-in before separation into individual dies and traditional packaging. Wafer-level burn-in has the advantages that failure-prone IC's are identified early, that for certain chip types (e.g., DRAM) there is the possibility of laser-repairing burn-in defects, and that wafer maps of burn-in failures are easily generated. Wafer maps assist in identifying and rectifying wafer processing flaws. Wafer-level burn-in has the disadvantages that careful handling of the wafer is required, and that making electrical contact with the wafer is more difficult. An example of a fixture used for wafer-level burn-in is shown in US Pat. No. 5,859,539 to Wood et al.
IC's also typically undergo functional tests at some point. These tests verify that the IC has the required functionality at the desired speed and accuracy. The functional tests can be used to reject IC's entirely, or may be used to classify IC's into different grades.
The cartridge of the invention may be used for wafer-level burn-in and/or testing.